1. Field of the Invention
This invention relates generally to semiconductor devices and process for fabricating the same and, particularly to a process for fabricating a flash EPROM or EEPROM memory device.
2. Description of the Related Art
Non-volatile memory devices, and particularly so-called "flash" memory devices, have become increasingly more popular in data storage applications. The term EPROM is an acronym for Erasable Programmable Read Only Memory, while EEPROM refers to Electrically Erasable PROMs. The term "flash" in conjunction with electrical erasable programmable read only memory or "flash EEPROMS", generally refers to EEPROM memory cells which are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. The operation and structure of such devices is discussed in U.S. Pat. No. 4,698,787, issued Oct. 6, 1987, to Mukherjee et al., and IEEE Journal of Solid State Circuitry, Vol. SC-22, No. 5, October, 1987, pages 676-683 in an article entitled, "A 128K Flash EEPROM Using Double Polysilicon Technology" by Gheorghe Samachisa, et al.
Generally, an array of flash EPROM or EEPROM memory cells may be formed on a semiconductor substrate in a series of rows and columns, accessed by conductors referred to as word lines and bit lines. A portion of an array is illustrated schematically in FIG. 1A. In FIG. 1A, a two-by-two matrix of memory cells 100 is shown with a first memory cell 20 having its drain connected to bit line 0 (BL0), its control gate coupled to word line 0 (WL0) and its source floating. Also shown in FIG. 1A is a second memory cell 22 also having its drain connected to BL0, its control gate coupled to word line 1 (WL1) and its source floating. As illustrated in FIG. 1A, the sources of the memory cells 20, 22, 24 and 26 are shown to be floating; however, the sources can be connected to form a common source line.
To program a cell, such as cell 20, the hot injection mechanism is normally induced by grounding the source region, applying a relatively high positive voltage (approximately 12V) to the control gate and applying a moderate voltage (approximately 5V or V.sub.cc) to the drain in order to generate high energy (hot) electrons. After sufficient negative charge accumulates onto the floating gate, the negative potential of the floating gate rises to a threshold voltage and inhibits current flow through the channel region during any subsequent read mode operation. Typically, in the read mode, a relatively low positive voltage, for example 1.5V, is applied to the drain, 5V or V.sub.cc is applied to the control gate and 0V is applied to the source of the memory cell. The magnitude of the read current is used in determining whether the flash EPROM or EEPROM cell is programmed or not.
Erasing flash EPROM or EEPROM cells is typically carried out by Fowler-Nordheim tunneling between the floating gate and the source (known as source erase or negative gate erase) or between the floating gate and the substrate (known as channel erase). The source erase operation is induced by applying a high positive voltage (approximately 12V) to the source region and 0V to both the control gate and the substrate, while floating the drain region of the memory cell. The negative gate erase operation is induced by applying 5V or V.sub.cc to the source region, and negative voltage (as much as -10V) to the control gate and 0V to the substrate, while floating the drain of the memory cell. The channel erase operation is induced by applying a high positive voltage (approximately 12V) to the substrate and 0V to the control gate, while floating both the source and drain of the memory cell.
As shown in FIG. 1B, in a memory device such as a flash EPROM or EEPROM, memory cells are arranged in a common region, with the memory cell region (a portion of which is shown in FIG. 1A) of the flash memory array being referred to as the "core" area of the chip. All other devices necessary for operation of the device, such as the select transistors and amplifiers, are located in the "periphery" area of the chip. In the core region, all memory cells have essentially the same dimensions, allowing simultaneous fabrication of the cells in the core region using common processing steps. Each memory cell is formed in the semiconductor substrate by, for example, diffusion of an n+ drain region, and an n type, double diffused source region, with a channel region positioned between the drain and source regions. The double diffused source region is formed of a deeply diffused, but lightly doped n type region, commonly doped with phosphorous (known as a double diffused junction (DDJ)), and a more heavily doped but more shallowly diffused n+ region, commonly doped with arsenic (As) within the DDJ. A tunnel oxide is formed on the silicon substrate separating a floating gate from the source and drain regions, and a control gate is formed over the floating gate, separated therefrom by an inter-polysilicon dielectric layer.
FIG. 2 illustrates a top view of a portion of a semiconductor substrate under fabrication as a flash cell, such as that shown schematically in FIG. 1A. Shown in FIG. 2 are two unit cells 20,22, formed by a second polysilicon gate layer or control gate layer 32 (defining wordline .o slashed. (WL.o slashed.)) deposited on top of an interdielectric layer 30 (shown in FIG. 5) such as oxinitride, and a first polysilicon gate layer or floating gate layer 29. Field oxide regions 42 formed by, for example, a LOCOS process, separate and isolates adjacent memory devices. A common source region 43 is used for adjacent cells and is formed by a self-aligned source mask and etch, as discussed below.
One conventional method of manufacturing a flash EPROM or EEPROM array includes a number of separate masking steps between the point in time when polysilicon layers (or "poly stack") which will form control gate and floating gate regions are deposited onto a substrate, and the steps of formation of the core memory devices. (It should be recognized that complete processing of the integrated circuit requires a substantial number of processing steps which are not detailed here in order not to unduly obscure the nature of the present invention. Such processing steps would be within the knowledge and skill of one of average skill in the art.)
In general, in one exemplary prior art process, the periphery devices are formed early in the process sequence, with the core region covered by a mask layer to prevent processing occurring in the periphery area from affecting the core area. After the periphery devices are formed, the masking over the core area is removed and the core area cells are formed, followed by junction implantation processing in the periphery area. The conventional process for forming the periphery cells requires the use of several masks to protect the core memory area from damage during its formation.
One portion of a conventional process flow which may be used for forming a memory array is illustrated in FIGS. 3-8. In FIGS. 3-8, the left side of each figure represents cross-sections of the core area (10), while the right side of each figure represents cross-sections of process steps occurring in the periphery area (12). FIGS. 7A and 7B illustrate the effects of identical process steps on different cross-sections of the device, represented along line A--A and B--B, respectively, in FIG. 2.
FIG. 3 shows a wafer substrate 50 having formed on it lateral isolation by, for example, a local oxidation of silicon (LOCOS) process growing select portions of a pad oxide resulting in field oxide regions 42.sub.1 -42.sub.2 (FIG. 2) and 42.sub.3 -42.sub.4 (FIG. 3). After formation of the field oxide regions, conventional polysilicon layer deposition and masking techniques will result in the provision of a first polysilicon layer 29 and an inter-polysilicon dielectric layer 30, overlying core region 10 of the array. A second polysilicon layer 32 is simultaneously deposited in both core region 10 and periphery region 12 of substrate 50. It should be recognized that polysilicon layers 29 and 32 may also be comprised of a polysilicide.
Once the polysilicon layers 29,32 are formed, the gate structures for cells in periphery area 12 are etched and prepared for junction implantation prior to formation of gate structures in core area 10.
FIGS. 4 and 5 show processing in the periphery region while the core is masked. A periphery gate photoresist layer 34 will be deposited on the surface of polysilicon layer 32 to cover the entire substrate. Next, layer 34 will be patterned by exposing resist layer 34 to a mask and, depending on whether a positive or negative resist is used, removing exposed or unexposed portions of the resist in the periphery area 12 leaving portions 34.sub.2. As shown in FIG. 4, masking layer 34 remains unpatterned in the core area 10. A periphery gate structure 36 will then be etched in periphery area 12, using any number of conventional anisotropic dry etch processes. Next, the remaining portions 34.sub.2 of resist layer 34 are stripped, leaving the gate structure shown in FIG. 5.
After the periphery devices are formed, the core device processing begins. Once the periphery gate devices 36 are formed, a core cell mask layer 40 will be applied to cover periphery area 12 and core area 10. As shown in FIG. 6, the core cell mask 40 is then patterned by exposing the resist and removing portions of the resist in core area 10, leaving selected portions 40.sub.1,40.sub.2. Core cell mask portions 40.sub.1,40.sub.2 are utilized to etch core cell gate structures 38,39 (shown in FIG. 7B). Core resist 40 will be stripped. Each gate structure 38,39 comprises a portion of first polysilicon layer 29, dielectric layer 30, and second polysilicon layer 32.
Next, isolation oxide 42.sub.1 will be etched to allow formation of a self-aligned source region 43, common to cells 101,102. FIGS. 7A and 7B show cross-sections of wafer formation along lines A--A and B--B, respectively, in FIG. 2. FIGS. 7A and 7B are provided to illustrate the effect of a self-aligned source mask and source etch, utilized in the prior art process, on the underlying substrate 50. Referring to FIG. 2, to form self-aligned source region 43, a portion of the field oxide region 42.sub.1 must be removed to expose substrate 50 in area 43 so that implantation and diffusion of, for example, an n type impurity may take place in the source region 43. This is conventionally known as the self-aligned source or "SAS" etch.
Referring to FIG. 7A, a self-aligned source photoresist mask layer (SAS mask) 41 is deposited over the surface of field oxide regions 42.sub.1-4 in the periphery and core areas, and patterned by mask exposure and resist stripping to expose a region 44 between adjacent second polysilicon layers 32 as shown in FIG. 7B. Field oxide 42.sub.1 -42.sub.12 is then etched using, for example, a reactive ion etch process to expose the surface of silicon substrate 50. As shown in FIG. 7B, in the pad oxide area, the SAS etch will remove not only portions of oxide layer 42.sub.1,42.sub.2 but also a small portion of substrate 50.
FIG. 7C depicts a cross-sectional side view of the gate stack 38 in a conventional flash cell and the damage done to the substrate 50 in the overlap area (shown to the left of line E) between the gate stack and the source area 43 caused by etching of source area 43 into the substrate 50. As seen in FIG. 7C, when the source area 43 is etched, layers of the substrate 50 are removed such that the source area no longer has a flat top surface but instead has a depressed top surface as shown by the dashed line D in FIG. 7C. After the etching of the source area 43, the damaged area of the substrate 50 is not limited to the top of the etched source area 43 but includes the area where the gate stack overlaps the source area 43. It is this area of damage present to the left of dashed line E that causes a variance in the V.sub.t characteristics of flash memory cells.
Generally, before memory cell 20 (FIG. 1A) can be programmed it must be erased along with all of the other memory cells within the matrix 100. Erasing of flash memory cells is typically performed by application of an erase voltage, as described above, to each of the memory cells over their respective control gates. After each application of an erase voltage, a verify voltage is applied to the memory cell to verify that the memory cell has actually been erased. If a particular memory cell does not conduct a current during the verify step, indicating that the memory cell is not fully erased, additional erasing voltages are applied until the memory cell conducts. Overerasing occurs because each application of the erase voltage removes electrons from the floating gate of the memory cells, including those cells that have been properly erased. When too many electrons have been removed, the floating gate becomes positively charged, thereby causing the overerase condition.
In order to read the contents of the memory cell 20 a voltage is applied to the drain of the programmed memory cell 20 and the contents of the cell are read onto BL0. At the same time, a small current I from erased memory cell 22 is also present on BL0. This small current, I, present on BL0 from memory cell 22 is what is known as column leakage and can promote serious errors in that the information present on BL0 will be incorrect. For example, in the situation described above, the information present on BL0 would be the information read from the programmed memory cell 20 and also include the leakage current I from memory cell 22. The column leakage current I, is a direct result of the variable V.sub.t characteristics between memory cell 20 and memory cell 22.
After the SAS etch is performed, resist layer 41 is stripped, leaving the structure shown in FIG. 8 prior to deposition of resist layer 45 for the double-diffusion implant.
In the conventional process, after the gate structures 38,39 are formed, impurities are provided into the substrate by implantation to form the source and drain regions. However, the SAS etch of the silicon on the surface of substrate 50 in region 44, as shown in FIGS. 7A and 7B, will result in the formation of polymers on the surface of substrate 50 which must be removed before any implantation or diffusion of impurities into substrate 50 can proceed. Thus, in the conventional process, a pre-implant oxidation step is required to cure and clean the surface of substrate 50 at area 43.
As shown in FIG. 8, after the pre-implant oxidation of substrate 50 and the oxide is stripped, a double diffusion implant photoresist mask 45 is formed over the surface of core area 10 and periphery area 12, patterned over core area 10 in region 442. An n type impurity such as phosphorous is implanted in the surface of substrate 50 using a low energy implant to form region 48 which serves as a portion of the common source. This is commonly referred to as the "DDI" (double diffusion implant). The low energy implant may be optionally followed by substrate heating to induce drive in of the impurities. The double diffusion implant mask 45 is then stripped.
Next, as shown in FIG. 9, a core n+ implant photoresist mask layer 47 is applied to the core area 10 and periphery area 12, and patterned using conventional photolithography techniques to expose areas of substrate 50 overlying source region 43 and drain regions 27,28 (FIG. 2). An n+ impurity implant is made into regions 27,28 and source region 43 to form n+ impurity region 46 and drain impurity regions 49.sub.1,49.sub.2 in substrate 50. After implantation of the n+ impurity regions 49.sub.1,49.sub.2 and 48, the core n+ implant mask 47 is stripped and processing on the core side 10 of the array is essentially completed. Processing of the integrated circuit to form other devices and structures necessary for the memory may proceed in accordance with well-known techniques.
For example, completion of the active devices in periphery region 12 will thereafter be performed. Generally, formation of the periphery transistors proceeds in accordance with well-known methods for forming lightly-doped drain transistors, which are summarized, (but not illustrated), by the following steps:
1. Performing a second pre-implant oxidation clean to remove n+ implant-formed polymers and removing the oxide. (A thicker oxide is grown in the core region to protect the core region during LDD implants); PA1 2. Forming an n type, lightly doped drain (LDD) implant photoresist mask layer and patterning the mask layer (in periphery area 12); PA1 3. Implanting an n type impurity to form n type, LDD regions and stripping the n type LDD resist; PA1 4. Forming a p type, LDD implant photoresist mask layer and patterning the mask layer; PA1 5. Implanting a p type impurity to form p type, LDD regions and stripping the p type LDD resist; PA1 6. Forming inert spacers for the n+ and p+ regions by depositing a spacer material and etching the spacer material; PA1 7. Performing a third pre-implant oxidation to clean substrate 50; PA1 8. Forming n type source/drain implant photoresist mask layer and patterning the mask layer; PA1 9. Implanting an n type impurity to form n+ source/drain regions, and stripping the photoresist; PA1 10. Forming a p type source/drain photoresist mask and patterning the resist; PA1 11. Implanting a p type impurity to form p+ source/drain regions, and stripping the resist; and, PA1 12. Oxidizing and/or annealing the source/drain regions.
After completion of the periphery transistors, contacts are formed utilizing conductive layers of metals or refractive metal silicides to complete formation of the integrated circuit device.
Thus, in the prior art, nine separate masking steps are required: the periphery gate mask; the core cell mask; the self-aligned source mask; the double-diffused implant mask; the core n+ implant mask; the n type LDD implant mask; the p type LDD implant mask; the n+ type source drain implant mask, and the p+ type source drain implant mask.